1. Field of the Invention
The present invention relates to the metallization of apertures to form void-free interconnections, including contacts or vias in high aspect ratio sub-half micron applications. More particularly, the present invention relates to a new metal nitride deposition process and apparatus.
2. Background of the Related Art
Sub-half micron multilevel metallization is one of the key technologies for the next generation of very large scale integration (xe2x80x9cVLSIxe2x80x9d). The multilevel interconnections that lie at the heart of the technology require planarization of high aspect ratio apertures, including contacts, vias, lines, or other features. Reliable formation of these interconnects is very important to the success of VLSI and to the continued effort to increase circuit density and quality of individual substrates and dies.
Physical vapor deposition (xe2x80x9cPVDxe2x80x9d) of aluminum (Al) or copper (Cu) is a common method to fill apertures. However, a problem with the PVD Al layer is the formation of voids which occur through a key hole process wherein the top portion of the via becomes sealed before the via has been entirely filled. As a consequence, as disclosed in U.S. Pat. No. 5,877,087 entitled xe2x80x9cLow temperature integrated metallization process and apparatusxe2x80x9d issued to Mosely et al. on Mar. 2, 1999 and as disclosed in its divisional United States patent application with an application Ser. No. 08/792,292 which are both incorporated herein by reference, a low temperature integrated metallization process has been developed to form void-free contacts or vias. The process comprises depositing a thin glue layer comprising a refractory metal. Possible glue layers include, but is not limited to, a titanium (Ti) and a titanium nitride (TiN) layer or a tantalum (Ta) and a tantalum nitride (TaN) layer. After the glue layer a conformal wetting layer of chemical vapor deposition (CVD) Al (or CVD Cu) is formed at low temperatures over the glue layer for the receipt of a layer of physical vapor deposition (xe2x80x9cPVDxe2x80x9d) Al (or PVD Cu) thereon. Then, a PVD Al (or PVD Cu) layer is deposited onto the previously formed CVD Al (or CVD Cu) layer at a temperature below that of the melting point temperature of Al (or Cu). This low temperature integrated metallization process results in a CVD/PVD Al (or Cu) layer that is substantially void-free.
However, a problem with this low temperature integrated metallization process is that high wiring resistance is found for features of dimensions less than 0.2 um. The high wiring resistance problem arises mainly with integrated circuit applications where sintering at 450xc2x0 Celsius for 30 minutes is performed upon completion of all process steps to repair any damage to the capacitors. There are three major causes of the high wiring resistance problem. First, the Ti/TiN layer readily decomposes and interacts at elevated temperatures (e.g. at 450xc2x0 Celsius) with an adjacent metal such as Al to form TiAlx. As a result of TiAlx formation on the sidewalls of apertures, the effective linewidth of the feature is reduced. Second, the TiN layer formed by metallo-organic chemical vapor deposition usually contains certain levels of impurities. At elevated temperatures, the impurities easily diffuse into the adjacent metal, which results in high resistivity. Third, the chemical vapor deposition of TiN using metallo-organic precusors forms a relatively thick layer of TiN on the sidewalls of apertures. This effectively reduces the line width of metal lines, especially for very thin lines.
Therefore, there is a need for a metallization process for creating line features that are void-free, have low resistivity, and greater effective line width. More particularly, it would be desirable to have a low temperature process for filling such contacts and vias with a glue layer and a metal layer where the glue layer does not react with the metal layer to form impurities, has fewer impurities that diffuse into the metal layer, and has less sidewall coverage of apertures.
The present invention generally provides improved metallization of apertures to form continuous, void-free interconnections with reduced resistivity and greater effective line width, including contacts or vias in high aspect ratio sub-half micron applications. More particularly, the present invention provides a low temperature process for filling such apertures with a glue layer and a metal layer where the glue layer does not react with the metal layer to form impurities, has fewer impurities that diffuse into the metal layer, and has less sidewall coverage of the apertures.
In one aspect of the invention, a refractory metal layer is deposited onto a substrate having high aspect ratio contacts or vias formed thereon. Next, a plasma-enhanced CVD (PECVD) refractory metal nitride layer is deposited on the refractory metal layer. Then, a metal layer is deposited over the metal nitride layer. PECVD of the metal nitride layer comprises contacting a plasma of a metal precursor gas, a nitrogen-containing gas, and a hydrogen-containing gas with the substrate to form a metal nitride layer. The deposited metal nitride layer is preferably treated with nitrogen plasma to densify the metal nitride film. The present invention reduces the interaction between the metal nitride layer and the metal layer at high temperatures because the PECVD metal nitride layer releases less impurities and has better microstructure compared to a metal nitride layer deposited by MOCVD. In addition, the metal layer has a lower resistivity because of the improved metal nitride layer. The resulting metal layer is substantially void free, has reduced resistivity, and has greater effective line width.
The present invention further provides an apparatus for providing improved step coverage and planarization of metal layers. The apparatus comprises an integrated processing system that generally includes various chambers so that once the substrate is introduced into a vacuum environment, the metallization of the vias and contacts occurs without exposure to possible contaminants.